Diodes: DC Analysis#

We can analyze circuits that include diodes using mesh and nodal analysis. Here, I favor using nodal as it extends more easily to circuits that include transistors as we will see in subsequent chapters. Most other texts use what I call “seat of the pants” circuit analysis for these circuits. I like to have a clear method for analysis rather than haphazardly applying the fundamental laws.

To apply nodal analysis to circuits with diodes, the three fundamental laws used in circuit analysis must remain usable:

  1. KVL - Still works!

  2. KCL - Still works!

  3. Ohm’s Law - Oops! Needs revision to work

Diode Volt/Amp Characteristic#

Ohm’s law as it was first introduced relates the voltage across and current through for a resistor.

\[V=IR\]

The previous chapter introduced the relationship between the voltage across a diode and current through the diode in the forward-bias region as

\[I_D=I_S\left(e^{\frac{V_D}{V_T}}-1\right)\]

Recall Nodal Analysis#

_images/recallNodal.svg
%% Recall Nodal Analysis
clear all
close all
clc
format short eng
format compact

syms Va Vb
e(1)=Va==5;
e(2)=((Va-Vb)/1e3)-((Vb)/500)==0;
sol=solve(e,Va,Vb);
Va=eval(sol.Va)
Vb=eval(sol.Vb)

Nodal Analysis with Nonlinear Diode Equation#

_images/nonlinearDiodeNodal.svg
%% Nodal Analysis with Nonlinear Diode Equation
clear all
close all
clc
format short eng
format compact

Is=1e-13;
Vt=26e-3;

syms Va Vb
e(1)=Va==5;
e(2)=((Va-Vb)/1e3)-Is*(exp(Vb/Vt)-1)==0;
sol=solve(e,Va,Vb);
Va=eval(sol.Va)
Vb=eval(sol.Vb)

More Nodes! More Regions!#

More complicated circuits have more non-ground nodes but the analysis is similiar. Remember, there is an underlying assumption we are making in this analysis. We assume the diode is operating in the forward-bias region

_images/nonlinearDiode3Nodes.svg
%% Nodal Analysis with Nonlinear Diode Equation: 3 Nodes
clear all
close all
clc
format short eng
format compact

Is=1e-13;
Vt=26e-3;

syms Va Vb Vc
e(1)=Va==5;
e(2)=((Va-Vb)/6)-Is*(exp(Vb/Vt)-1)-((Vb-Vc)/3)==0;
e(3)=((Vb-Vc)/3)+1==0;
sol=solve(e,Va,Vb,Vc);
Va=eval(sol.Va)
Vb=eval(sol.Vb)
Vc=eval(sol.Vc)
Vd=Vb

Bad Assumptions, Bad Results#

What do the results look like if the assumption is bad? How will we know the assumption is bad? We can easily break our forward-bias assumption by flipping the diode in the circuit. Take note that I also flipped the current and voltage directions for the diode.

_images/nonlinearDiode3NodesBadAss.svg
%% Nodal Analysis with Nonlinear Diode Equation: 3 Nodes, Bad Assumption
clear all
close all
clc
format short eng
format compact

Is=1e-13;
Vt=26e-3;

syms Va Vb Vc
e(1)=Va==5;
e(2)=((Va-Vb)/6)+Is*(exp(-Vb/Vt)-1)-((Vb-Vc)/3)==0;
e(3)=((Vb-Vc)/3)+1==0;
sol=solve(e,Va,Vb,Vc);
Va=eval(sol.Va)
Vb=eval(sol.Vb)
Vc=eval(sol.Vc)
Vd=0-Vb

Load Lines#

Good Assumption#

_images/loadLineDiodeGood.svg

Bad Assumption#

_images/loadLineDiodeBad.svg

Pros and Cons of Load Lines#

Making Linear Assumptions#

Forward-bias Assumption#

Reverse-bias Assumption#

Breakdown Assumption#

Example#

_images/linearAssumptionsDiode.svg
%% Assume forward-bias
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Id
e(1)=Va==10;
e(2)=Va-Vb==0.7;
e(3)=((Vb-Vc)/3)+5==0;
e(4)=Id-((Vb)/6)-((Vb-Vc)/3)==0;
sol=solve(e,Va,Vb,Vc,Id);
Id=eval(sol.Id)
%% Assume reverse-bias
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc
e(1)=Va==10;
e(2)=-((Vb)/6)-((Vb-Vc)/3)==0;
e(3)=((Vb-Vc)/3)+5==0;
sol=solve(e,Va,Vb,Vc);
Vd=eval(sol.Va-sol.Vb)
%% Assume breakdown
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Id
e(1)=Va==10;
e(2)=Va-Vb==-60;
e(3)=((Vb-Vc)/3)+5==0;
e(4)=Id-((Vb)/6)-((Vb-Vc)/3)==0;
sol=solve(e,Va,Vb,Vc,Id);
Id=eval(sol.Id)

Example#

_images/linearAssumptionsDiode2.svg
%% Assume forward
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Id
e(1)=0-Vb==0.7;
e(2)=Va-Vb==6;
e(3)=((Vb-Vc)/6e3)-((Vc)/12e3)+((Va-Vc)/4e3)==0;
e(4)=-Id+((Va)/9e3)+((Vc)/12e3)==0;
sol=solve(e,Va,Vb,Vc,Id);
Id=eval(sol.Id)
%% Assume reverse
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc
e(1)=Va-Vb==6;
e(2)=-((Va)/9e3)-((Va-Vc)/4e3)-((Vb-Vc)/6e3)==0;
e(3)=((Vb-Vc)/6e3)-((Vc)/12e3)+((Va-Vc)/4e3)==0;
sol=solve(e,Va,Vb,Vc);
Vd=eval(0-sol.Vb)
%% Assume breakdown
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Id
e(1)=0-Vb==-20;
e(2)=Va-Vb==6;
e(3)=((Vb-Vc)/6e3)-((Vc)/12e3)+((Va-Vc)/4e3)==0;
e(4)=-Id+((Va)/9e3)+((Vc)/12e3)==0;
sol=solve(e,Va,Vb,Vc,Id);
Id=eval(sol.Id)

Example#

_images/linearAssumptionsDiode3.svg
%% Assume forward
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Vd Id
e(1)=Va==20;
e(2)=Va-Vb==0.7;
e(3)=6+((Vb-Vd)/2)==0;
e(4)=((Vb-Vc)/10)-((Vc)/4)==0;
e(5)=Id-((Vb-Vd)/2)-((Vb-Vc)/10)==0;
sol=solve(e,Va,Vb,Vc,Vd,Id);
Id=eval(sol.Id)
%% Assume reverse
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Vd
e(1)=Va==20;
e(2)=-((Vb-Vd)/2)-((Vb-Vc)/10)==0;
e(3)=6+((Vb-Vd)/2)==0;
e(4)=((Vb-Vc)/10)-((Vc)/4)==0;
sol=solve(e,Va,Vb,Vc,Vd);
Vd1=eval(sol.Va-sol.Vb)
%% Assume breakdown
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Vd Id
e(1)=Va==20;
e(2)=Va-Vb==-60;
e(3)=6+((Vb-Vd)/2)==0;
e(4)=((Vb-Vc)/10)-((Vc)/4)==0;
e(5)=Id-((Vb-Vd)/2)-((Vb-Vc)/10)==0;
sol=solve(e,Va,Vb,Vc,Vd,Id);
Id=eval(sol.Id)

Example#

_images/linearAssumptionsDiode4.svg
%% Assume forward
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Vd Id
e(1)=Va==12;
e(2)=Va-Vd==0.7;
e(3)=Vb-Vc==12;
e(4)=((Va-Vb)/4e3)+6e-3-((Vc)/4e3)==0;
e(5)=Id-6e-3-((Vd)/4e3)==0;
sol=solve(e,Va,Vb,Vc,Vd,Id);
Id=eval(sol.Id)
%% Assume reverse
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Vd
e(1)=Va==12;
e(2)=Vb-Vc==12;
e(3)=-((Vd)/4e3)-6e-3==0;
e(4)=((Va-Vb)/4e3)+6e-3-((Vc)/4e3)==0;
sol=solve(e,Va,Vb,Vc,Vd);
Vd1=eval(sol.Va-sol.Vd)
%% Assume breakdown
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Vd Id
e(1)=Va==12;
e(2)=Va-Vd==-100;
e(3)=Vb-Vc==12;
e(4)=((Va-Vb)/4e3)+6e-3-((Vc)/4e3)==0;
e(5)=Id-6e-3-((Vd)/4e3)==0;
sol=solve(e,Va,Vb,Vc,Vd,Id);
Id=eval(sol.Id)

Multiple Diode Circuits#

Example#

_images/multipleDiodes01.svg
%% Assume D1 - forward, D2 - forward
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Vd Id1 Id2
e(1)=Va==10;
e(2)=Vd==3;
e(3)=Vb-Vc==0.7;
e(4)=Vd-Vc==0.7;
e(5)=((Va-Vb)/4e3)-Id1==0;
e(6)=Id1+Id2-((Vc)/6e3)==0;
sol=solve(e,Va,Vb,Vc,Vd,Id1,Id2)
Id1=eval(sol.Id1)
Id2=eval(sol.Id2)
%% Assume D1 - forward, D2 - reverse
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Vd Id1 Id2
e(1)=Va==10;
e(2)=Vd==3;
e(3)=Vb-Vc==0.7;
e(4)=((Va-Vb)/4e3)-Id1==0;
e(5)=Id1-((Vc)/6e3)==0;
sol=solve(e,Va,Vb,Vc,Vd,Id1,Id2)
Id1=eval(sol.Id1)
Vd2=eval(sol.Vd-sol.Vc)
%% Assume D1 - reverse, D2 - reverse
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Vd Id1 Id2
e(1)=Va==10;
e(2)=Vd==3;
e(3)=((Va-Vb)/4e3)==0;
e(4)=((Vc)/6e3)==0;
sol=solve(e,Va,Vb,Vc,Vd,Id1,Id2)
Vd1=eval(sol.Vb-sol.Vc)
Vd2=eval(sol.Vd-sol.Vc)
%% Assume D1 - reverse, D2 - forward
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Vd Id1 Id2
e(1)=Va==10;
e(2)=Vd==3;
e(3)=Vd-Vc==0.7;
e(4)=((Va-Vb)/4e3)==0;
e(5)=Id2-((Vc)/6e3)==0;
sol=solve(e,Va,Vb,Vc,Vd,Id1,Id2)
Vd1=eval(sol.Vb-sol.Vc)
Id2=eval(sol.Id2)

Example#

_images/multipleDiodes02.svg
%% Assume D1 - forward, D2 - forward
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Vd Ve Id1 Id2
e(1)=Va==6;
e(2)=Vb-Vd==0.7;
e(3)=Ve-Vc==0.7;
e(4)=((Va-Vb)/12e3)-((Vd)/6e3)-((Vb-Vc)/2e3)==0;
e(5)=((Vb-Vc)/2e3)-((Ve)/4e3)+1e-3==0;
e(6)=Id1-((Vd)/6e3)==0;
e(7)=-Id2-((Ve)/4e3)==0;
sol=solve(e,Va,Vb,Vc,Vd,Ve,Id1,Id2)
Id1=eval(sol.Id1)
Id2=eval(sol.Id2)
%% Assume D1 - forward, D2 - reverse
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Vd Ve Id1
e(1)=Va==6;
e(2)=Vb-Vd==0.7;
e(3)=((Va-Vb)/12e3)-((Vd)/6e3)-((Vb-Vc)/2e3)==0;
e(4)=((Vb-Vc)/2e3)+1e-3==0;
e(5)=Id1-((Vd)/6e3)==0;
e(6)=((Ve)/4e3)==0;
sol=solve(e,Va,Vb,Vc,Vd,Ve,Id1)
Id1=eval(sol.Id1)
Vd2=eval(sol.Ve-sol.Vc)
%% Assume D1 - reverse, D2 - reverse
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Vd Ve
e(1)=Va==6;
e(2)=((Va-Vb)/12e3)-((Vb-Vc)/2e3)==0;
e(3)=((Vb-Vc)/2e3)+1e-3==0;
e(4)=((Vd)/6e3)==0;
e(5)=((Ve)/4e3)==0;
sol=solve(e,Va,Vb,Vc,Vd,Ve)
Vd1=eval(sol.Vb-sol.Vd)
Vd2=eval(sol.Ve-sol.Vc)
%% Assume D1 - reverse, D2 - forward
clear all
close all
clc
format short eng
format compact

syms Va Vb Vc Vd Ve Id2
e(1)=Va==6;
e(2)=Ve-Vc==0.7;
e(3)=((Va-Vb)/12e3)-((Vb-Vc)/2e3)==0;
e(4)=((Vb-Vc)/2e3)-((Ve)/4e3)+1e-3==0;
e(5)=-((Vd)/6e3)==0;
e(6)=-Id2-((Ve)/4e3)==0;
sol=solve(e,Va,Vb,Vc,Vd,Ve,Id2)
Vd1=eval(sol.Vb-sol.Vd)
Id2=eval(sol.Id2)